1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a current mirror circuit. Especially, the invention is directed to a current mirror circuit which employs an integrated injection logic circuit (I.sup.2 L).
2. Description of the Prior Art
The I.sup.2 L circuit is a new logical circuit which was described, for example, in a published article by H. H. Benger and S. K. Wiedman: Merged-Transistor Logic (MTL)--A Low-Cost Bipolar Logic Concept; IEEE J. of SSC, sc-7, 5, pgs 340-346 (1972, Oct.), and a publication by K. Hart and A. Slob: Integrated Injection Logic: A New Approach to LSI; IEEE J. of SSC, sc-7, 5, pgs 346-351 (1972, Oct.). The I.sup.2 L circuit has attracted attention for such reasons as capability of a high density of integration, wide application, and capability of coexistence with conventional bipolar transistors.
FIG. 1A shows an equivalent circuit diagram of an I.sup.2 L circuit, while FIG. 1B shows a sectional structure of the elements. As illustrated in FIG. 1A, the I.sup.2 L circuit may be considered as a combination of a common base PNP transistor 11 and a common emitter NPN transistor 12. The emitter I of the transistor 11 is usually called the "injector", and a power supply is connected to this terminal. The base B of the transistor 12 is used as an input terminal, and the collectors C.sub.1 through C.sub.3 are used as output terminals, so as to derive multi-collector outputs. The transistor 12 is such that the emitter and collector of a conventional planar transistor are inverted, and the emitter E is grounded. The configuration described above is apparent from the sectional view of FIG. 1B.
The PNP transistor 11 is constructed of a lateral transistor, the emitter of which is formed of a P-type semiconductor region 13, the base of which is formed of an epitaxially grown semiconductor layer of N-type conductivity 14, and the collector of which is formed of a P-type semiconductor region 15. The NPN transistor 12 is constructed with the collectors formed of N-type semiconductor regions 16, the base formed of the P-type semiconductor region 15, and the emitter formed of the N-type epitaxial semiconductor layer 14. A buried layer of N.sup.+ -type conductivity 191 and a semiconductor region of N.sup.+ -type conductivity 192 serve to lead out a common ground terminal. The region 192 is also called a "collar region of N.sup.+ -conductivity" for preventing the influence of parasitic transistors. In addition to contacting the region 191, the region 192 is sometimes formed with a shallow portion so as to surround the I.sup.2 L element.
Shown at 10 is a semiconductor substrate of P-type conductivity. The substrate 10 is a silicon (Si), substrate, and the semiconductor layer 14 is an Si epitaxial layer. The semiconductor regions 13, 15, 16, 191, and 192 are formed by thermal diffusion, ion implantation, etc.
As is seen from FIG. 1B, the collector of the PNP transistor 11 and the base of the NPN transistor 12 are formed by P-type semiconductor region 15. The base of the PNP transistor 11 and the emitter of the NPN transistor 12 are formed by the N-type epitaxial layer 14 in common.
The I.sup.2 L element described above has a small occupying area, is capable of a low power operation, and is easily brought into coexistence with other functional circuits employing bipolar transistors, so that it is being applied extensively. However, when it coexists with the other functional circuits employing bipolar transistors, the area of the circuit portion other than the I.sup.2 L element is large and the power dissipation thereof is high, and the features of the I.sup.2 L element are often decreased along with the whole LSI.
When injector current of the I.sup.2 L element must be a minute current, a current mirror circuit is often employed as current supplyng means, in order to supply a constant current. A "current mirror circuit" is a circuit which provides a current equal to a certain reference current (given current) from an output terminal. Where the current mirror circuit is constructed of a multi-collector transistor, currents which correspond to the area ratios of the respective collectors can be supplied.
A prior art current mirror circuit is shown in FIG. 2A. In this circuit, current I.sub.21 which is derived from collectors C.sub.4 and C.sub.5 is equal to current I.sub.22 which flows through a resistor R. When using this circuit as a current source for supplying a low current (approximately several .mu.A or less), the resistor R requires a great resistance value (several hundreds K.OMEGA. or above). With ordinary bipolar transistor processes, accordingly, a pinch resistor must be used. The pinch resistor, however, has disadvantages that the area is large, the temperature dependence is inferior, and a large margin is required for design because of large dispersion and an inferior precision.
FIG. 2B shows a plan pattern when the circuit of FIG. 2A is constructed of an integrated circuit. A P-type region 21, an N-type region 22, and P-type regions 23, 24, and 25 become the emitter, the base, and the collectors of a multi-collector PNP transistor 201, respectively. A P-type region 26, an N-type region 27, and a P-type substrate 28 become the emitter, base, and collector of a PNP transistor 202, respectively. Regions 291 and 292 (part of the one-dot chain line) are P-type and N-type regions respectively, which constitute the pinch resistor. Parts of broken lines are metallic interconnections.
As is apparent from FIG. 2B, the pinch resistor occoupies most of the region of the current mirror circuit. By way of example, when a current of 1.mu.A is to be derived from the collectors C.sub.4 and C.sub.5 with V.sub.CC= 5V, the resistance of the resistor R must be about 4M.OMEGA.. Therefore, the occupying area of the resistor part only becomes 310=180.mu.m.sup.2, which is very unfavorable.